1. Field of the Invention
The present invention relates to a semiconductor device test board and an evaluation test method and particularly to an improvement which enables a time-saving, effective evaluation test of semiconductor devices.
2. Description of Related Art
FIG. 8 is a flowchart showing a conventional evaluation test method carried out after assembling semiconductor devices. In FIG. 8, ST1 designates an evaluation test step of evaluating fundamental electrical of characteristics, such as DC (direct current) characteristics; ST2 designates a first quality check step of screening out defective unit identified in the electrical characteristic evaluation test step ST1; ST3 designates a burn-in step of forcedly inducing early failures by putting the semiconductor devices identified as non-defectives in the first quality check step ST2 in a burn-in oven providing a high temperature environment; ST4 designates a performance check evaluation test step of checking performance of the semiconductor devices which have undergone the burn-in procedure by supplying the semiconductor devices with predetermined signal patterns from an LSI tester or the like; and ST5 is a second quality check step of screening out defective unit identified in the performance check evaluation test step ST4.
With a sharp increase of integration density in recent years, the time period consumed by the performance check evaluation test step has markedly increased, and hence effective evaluation test is of critical importance to determining the productivity of semiconductor devices.
FIG. 9 is a block diagram showing a conventional burn-in system improved considering such a situation. In FIG. 9, reference numerals 1 each designate a semiconductor device to be evaluated; 2 each designate a burn-in board (test board) on which a plurality of semiconductor devices 1 are mounted. The reference numeral 3 designates a burn-in oven for containing the burn-in boards 2; 4 designates a power supply embedded in the burn-in oven 3 for supplying power to the burn-in boards 2; and 5 designates an LSI tester provided outside of the burn-in oven 3 for supplying the semiconductor devices on each burn-in board 2 with predetermined test patterns through signal lines, and for retaining results of the test.
With such a burn-in system, it is possible to carry out the performance check by supplying the test signals from the LSI tester 5 to individual semiconductor devices 1 while they are subject to the burn-in process in the burn-in oven 3. Thus, the present burn-in system enables a part of the performance check evaluation test step ST4 in FIG. 8 to be achieved in parallel with the burn-in step ST3, thereby achieving effective evaluation test of the semiconductor devices 1.
Japanese patent application laid-open No. 1-277779/1989 discloses an evaluation test method which simplifies the burn-in system by integrating the functions of the LSI tester 5 into each semiconductor device, and thus reduces cost and evaluation steps. It also discloses a system including thyristors and lamps mounted on the burn-in board. Each thyristor, driven by a signal output from one of the semiconductor devices as a result of the test, turns on the lamp connected to each thyristor once a failure has occurred in the semiconductor device, and keeps the lamp illuminated even if the semiconductor device recovers from the failure during the burn-in process. This makes it possible to check the result of the performance test of the individual semiconductor devices.
With such an arrangement, the conventional burn-in system has a problem in that the test result cannot be checked after the burn-in boards 2 are taken out of the burn-in oven 3. This is because the semiconductor devices are disconnected from the power supply 4, and hence the lamps cannot keep the results of the test. Thus, a new step becomes necessary of separating the non-defective from the defective unit by observing the test results before taking the burn-in boards 2 out of the burn-in oven 3. This will increase the number of steps of the evaluation test and labor (man-power). As a result, an expected improvement in efficiency cannot be achieved considering the evaluation test in its entirety.